1. Field of the Invention
The present invention relates to read/write memory arrays, and more particularly to those arrays having multiple read/write ports thereto.
2. Description of the Related Art
In a traditional single-port memory array, a single address is presented to the array, and a memory cell identified by that address is either written with data presented to the port, or is read from the array and thus drives data outputs corresponding to the port. The single address may include a large number of individual address bits to fully specify each of the individual memory cells in the array. For example, a 20-bit address is required for a 1 megabit memory array which has a single data input/output bit (a 1MB.times.1 memory array). The number of memory cells selected by a particular address may be one, as in the above example, or may be more than one. Memory arrays which simultaneously address, for example, eight bits of data are frequently desirable to increase the amount of data which is either read or written during each memory operation. In such a "byte-wide" memory array eight memory cells are simultaneously selected for each particular address presented to the port. In a write cycle (i.e., write operation) each of the selected memory cells is written with a respective one of eight bits of data presented to the port. Conversely, in a read cycle (i.e., read operation) each of eight data outputs for the port is driven with data read from a respective one of the eight selected memory cells. Memory arrays as discussed above may be configured as part of a commodity memory product (such as the well known products of the type typically incorporated into a memory SIMM for a personal computer), or may be configured as part of a larger system, such as a processor, cache subsystem, DMA channel, network interface, or a wide variety of other systems or subsystems.
While the great bulk of memory used today is configured with a single port as described above, memory arrays which are addressed independently by more than one port, known as multi-port memory arrays, are increasingly used by system architects to achieve a variety of performance and/or functionality goals. For example, dual-port memory arrays are frequently used as buffers between two subsystems which are asynchronous to each other. FIFO's (first-in-first-out buffers) are specialized sequentially-accessed dual-port memories. Moreover, memories specially adapted for frame memory within a video system (e.g., VRAMs) allow simultaneous and independent access by both a processor as well as a video subsystem so that each is not interrupted when the other accesses the memory array. A register file of a processor may be configured with two read ports and one write port, so that two operands for a pending operation may be simultaneously retrieved while a result from a completed operation is written. Other sophisticated applications continue to require an even greater number of ports into a memory array. Achieving additional ports in a memory array has traditionally resulted in a significant penalty in chip area or die size (the layout size of the memory array) as well as a penalty in performance of the memory array. To achieve large numbers of ports, high-density high-performance memory array structures cannot be used, and structures resembling a logic gate implementation of the memory array are frequently used instead.
A traditional "4T-2R" single-port static memory cell (also sometimes known as a "4T" cell) is depicted in FIG. 1. Two cross-coupled N-channel transistors (transistors 116 and 118) form the basic storage element of the memory cell 101. These transistors 116 and 118 couple internal nodes 108 and 110, respectively, to a common terminal 100 which is typically connected to receive a reference voltage such as electrical ground. For descriptive convenience, such a common terminal 100 is commonly referred to as a ground terminal, and will hereinafter be referred to as ground terminal 100. Resistors 120 and 122 couple internal nodes 108 and 110, respectively, to a power supply terminal 105 which is typically connected to receive a positive power supply voltage which may typically be in the several volt range, with 3.3 volts and 5.0 volts being common examples. Such a positive power supply voltage is frequently referred to as a V.sub.DD voltage, and for descriptive convenience the power supply terminal 105 will hereinafter be referred to as V.sub.DD terminal 105. The resistors 120 and 122 are typically implemented using a high resistivity polysilicon film which is largely stacked above the transistors of the memory cell which are implemented in lower semiconductor layers. Consequently, use of such resistors 120 and 122 results frequently in a smaller memory cell layout than an alternative "6T" memory cell design which uses P-channel transistors for the load elements (See FIG. 3 and related discussion hereinafter). The two resistors 120 and 122 are designed to be extremely high magnitude resistors in order to minimize the static current flow (i.e., the "DC" current) through the memory cell 101.
The internal nodes 108 and 110 of the memory cell 101 are coupled through a pair of N-channel access transistors 112 and 114 to a pair of respective bit lines 104 and 106. These bitlines 104 and 106 are used for both reading and writing the memory cell 101 when the wordline 102 is enabled and provide for a single data port into the memory cell 101. One of the bitlines, such as bitline 104, is commonly referred to as the true bitline 104 and the other bitline, such as bitline 106, is commonly referred to as the complement bitline 106. Since the cell is symmetrical, such a designation is arbitrary at the cell level and in practice may result from product data polarity designations or designer preference. For convenience, the pair of bitlines 104 and 106 may hereinafter also be referred to as the true bitline 104 and the complement bitline 106. The operation of a such a memory cell 101 depicted in FIG. 1 is well known by those skilled in the art.
A traditional "4T-2R" dual-port static memory cell 151 is depicted in FIG. 2. As before, two cross-coupled N-channel transistors (transistors 166 and 168) form the basic storage element of the memory cell 151. These transistors 166 and 168 couple internal nodes 158 and 160, respectively, to the ground terminal 100. Resistors 170 and 172 couple internal nodes 158 and 160, respectively, to the V.sub.DD terminal 105. The resistors 170 and 172 are likewise typically implemented using a high resistivity polysilicon film and are designed to be extremely high magnitude resistors.
The internal nodes 158 and 160 of the memory cell 151 are coupled through a first pair of N-channel access transistors 162 and 164 to a first pair of bit lines 154 and 156, and are also coupled through a second pair of N-channel access transistors 163 and 165 to a second pair of bit lines 155 and 157. The first pair of bitlines 154 and 156 is used for both reading and writing the memory cell 151 when a first wordline 152 is enabled, and together provide for a first data port into the memory cell 151. The second pair of bitlines 155 and 157 is similarly used for both reading and writing the same memory cell 151 when a second wordline 153 is enabled, and together provide for a second data port into the same memory cell 151 . For convenience, the first pair of bitlines 154 and 156 may hereinafter also be individually referred to as the port 1 true bitline 154 and the port 1 complement bitline 156, respectively. Furthermore, the second pair of bitlines 155 and 157 may hereinafter also be individually referred to as the port 2 true bitline 155 and the port 2 complement bitline 157, respectively.
An alternative arrangement of a dual-port static memory cell is depicted in FIG. 3. Memory cell 151a has load elements fashioned from a pair of cross-coupled P-channel transistors rather than from high value polysilicon resistors. Cross-coupled P-channel transistors 174 and 176 couple internal nodes 158a and 160a, respectively, to the V.sub.DD terminal 105. As mentioned before, such a cell traditionally results in a larger cell layout not only due to the inclusion of two additional transistors, but also due to the requirement for providing N-well to P-well isolation within each memory cell of a memory array. Potential advantages of P-channel loads for a multi-port memory cell are discussed further herebelow.
A four-port memory cell having resistor loads is depicted in FIG. 4 as memory cell 201. It should be noted that such a four-port memory cell 201 has not been successfully implemented, although it is seemingly a straightforward extension of the two-port memory cell 151 shown in FIG. 2, for the reasons to be described below (and potentially for other reasons, as well). As before, two cross-coupled N-channel transistors 216 and 218 form the basic storage element of the memory cell 201 and couple internal nodes 208 and 210, respectively, to the ground terminal 100. Resistors 220 and 222 couple the internal nodes 208 and 210, respectively, to the V.sub.DD terminal 105. The resistors 220 and 222 are likewise typically implemented using a high resistivity polysilicon film and are designed to be extremely high magnitude resistors.
The internal nodes 208 and 210 of the memory cell 201 are coupled through a first pair of N-channel access transistors 212.1 and 214.1 to a first pair of bit lines 204.1 and 206.1, thus forming a first port. A second pair of N-channel access transistors 212.2 and 214.2 couples the internal nodes 208 and 210, respectively, to a second pair of bit lines 204.2 and 206.2, thus forming a second port. A third pair of N-channel access transistors 212.3 and 214.3 couples the internal nodes 208 and 210, respectively, to a third pair of bit lines 204.3 and 206.3, thus forming a third port. Lastly, a fourth pair of N-channel access transistors 212.4 and 214.4 couples the internal nodes 208 and 210, respectively, to a fourth pair of bit lines 204.4 and 206.4, thus forming a fourth port. A first wordline 202.1 is connected to the gate terminal of access transistors 212.1 and 214.1 to control the first port. Similarly, additional wordlines 202.2, 202.3, and 202.4 control the second, third, and fourth ports, respectively. Referring to the first port, the bitlines 204.1 and 206.1 may be defined to be the true and complement bitlines, respectively, for port 1, and for convenience may also be referred to as bitlines BL.sub.-- P1 and XBL.sub.-- P1 (the initial character "X" implying the complement polarity). Similarly, the bitlines 204.2 and 206.2 would follow as true and complement bitlines, respectively, for port 2, and may be referred to as bitlines BL.sub.-- P2 and XBL.sub.-- P2; bitlines 204.3 and 206.3 would follow as true and complement bitlines, respectively, for port 3, and may be referred to as bitlines BL.sub.-- P3 and XBL.sub.-- P3; and bitlines 204.4 and 206.4 would follow as true and complement bitlines, respectively, for port 4, and may be referred to as bitlines BL.sub.-- P4 and XBL.sub.-- P4.
A well designed memory cell (having an adequately high ratio of the cross-coupled transistors (e.g., transistor 218) to the access transistors (e.g., transistor 214.4)) is usually able to be read by virtually any number of read ports. However, a significant problem materializes as the number of ports which can write to the cell increases. This can be illustrated by first assuming that a logical "0" is stored within the memory cell 201. This results in a low voltage, V.sub.LO, on internal node 208, and a high voltage, V.sub.HI, on internal node 210, as indicated in FIG. 4. Next assume that ports 1, 2, and 3 are enabled to read the memory cell, while port 4 is enabled to write a logical "1" (being opposite data to that previously stored) into the memory cell 201. To write a logical "1" through port 4, bitline BL.sub.-- P4 is driven high and bitline XBL.sub.-- P4 is driven low. Since all 4 ports are active, all four wordlines 202.1, 202.2, 202.3, and 202.4 are active and thus driven high. A write current, I.sub.WR, flows from internal node 210 through access transistor 214.4 to the bitline XBL.sub.-- P4 to cause the memory cell 201 to change states. Such a state change occurs when the voltage on internal node 210 decreases sufficiently to turn transistor 216 substantially off, thus allowing access transistor 212.4 to charge internal node 208 to a higher voltage. Such a high voltage on internal node 208 turns on transistor 218 and causes the voltage of internal node 210 to remain well below the threshold voltage of transistor 216, even after the write operation has concluded and the access transistors 212.4 and 214.4 have turned off. The voltage of internal node 210 must be driven to a rather low voltage for transistor 216 to begin to turn off, which is necessary before the cell data can switch states.
Achieving a sufficiently low voltage on internal node 210 is made more difficult by the simultaneous reading of the same memory cell 201 through port 1, port 2, and port 3, however. As internal node 210 falls in voltage, a read current, I.sub.RD, flows from bitline XBL.sub.-- P1 through access transistor 214.1 to internal node 210. Likewise, a read current, I.sub.RD, also flows from bitline XBL.sub.-- P2 through access transistor 214.2, and from bitline XBL.sub.-- P3 through access transistor 214.3, all as shown in FIG. 4. The source of this read current I.sub.RD is two-fold. A first component originates from each of the bitline load devices 230 connected to each of the bitlines. But even if such load devices 230 are made smaller, a second component arises from the capacitance of the bitlines themselves. In the above example, each of bitlines XBL.sub.-- P1, XBL.sub.-- P2, and XBL.sub.-- P3 would have to be significantly discharged by the read current I.sub.RD before the memory cell 201 is written to a logical "1," and all of the current to discharge the three bitlines which are engaged in reading must be conducted through access transistor 214.4. This results in a huge variation in the write time of a cell depending upon the number of other ports which are reading the same cell. Moreover, the conditions described in the example above are true not only for other read ports accessing the same cell, but are also true for any other cell sharing the same wordlines: that is, whenever the row address of a port which is reading is the same as the row address of a port that is writing, even if the column addresses are different. Such a problem may be called row contention of a multi-port array.
As additional ports are added to a memory cell, it is possible that a single write port is unable to sufficiently discharge a cell to ever write the data, no matter how much time is allowed for the discharging of bitlines associated with ports which are reading. This occurs when the effective voltage divider formed between access transistors which are reading (in the above example, e.g., access transistors 214.1, 214.2, and 214.3 acting in parallel) and the access transistor which is writing (e.g., access transistor 214.4) is insufficient to drive the internal node of the memory cell (e.g., internal node 210) below the trip point of the memory cell.
This row contention phenomenon may be reduced by utilizing a memory cell having P-channel load devices, analogous to that shown in FIG. 3, because the trip point of such a memory cell can be made to be higher than a memory cell utilizing high resistance polysilicon load resistors. But the lengthening of write timing due to the necessary discharging of bitlines associated with ports which are reading still creates a tremendously undesirable characteristic for a user of the multi-port memory array to deal with.
What is needed is a memory structure which can support additional numbers of ports without either a static write incapability, nor a dynamic write timing penalty when row addresses on multiple ports happen to match. What is needed, in other words, is a memory structure which eliminates row contention.